1. Field of Invention
The invention relates to a data processing device and method and, in particular, to a device and method, which can reduce the accessing time when a processor accesses digital data from a register.
2. Related Art
In the recent years, human beings have entered the information time. The computer technology has well and fast developed, so that the digital products are flooded in our daily lives. Most people have one personal computer for dealing with their businesses and privacies. For example, they can use the computer to handle with many documents. For the entertainment purpose, the computer can be used to browse Internet or to play video medium.
The major elements of the computer include a processor, a storage unit and registers. In the view of the computer, it can only process the digital data. For instance, the computer can retrieve a video file and display it on the screen, or access data from an external storage media, process the data and then store the data in a hard drive. Both the data stored in the hard drive and the data accessed from the external storage media are temporarily stored in the registers for waiting the processor to read and process them.
In general, the processor of a multiplex operation system possesses the ability of sorting multiple procedures. When one procedure requests data from the register of the data processing device, it is desired to provide some solutions for the situation that the data are not prepared.
There are two conventional solutions as shown in FIG. 1 and FIG. 2 for the situation that the data of the register are not prepared. As shown in FIG. 1, the step S10 shows that the data to be processed are stored in the register and the processor is accessing the data from the register. The step S12 determines whether the data of the register are valid or not. When the data of the register are totally accessed by the processor and no new data is recorded in the register, the step S12 determines that the data of the register are invalid and the step S14 is performed. When the data of the register are sufficient for the processor, the step S12 determines that the data of the register are valid and the step S10 is then performed. The step S14 shows that the processor is in an inquiring state. In this case, the processor should check whether the register has new data for accessing all the time. In brief, the processor will wait for the register until the new data are recorded in the register, and then the step S10 can be performed. As mentioned above, this solution has one undesired problem. That is, in a procedure of accessing the register within a multiplex operation system environment, the processor will stay in the inquiring state as the data of the register are invalid. Thus, the processor may waste a lot of time on this inquiring state, and, relatively, spend fewer time on processing other procedures.
As shown in FIG. 2, the step S20 shows that the data to be processed are stored in the register and the processor is accessing the data from the register having an assumed capacity of 32 bytes. After the processor accesses through the 32 bytes data, the step S22 is performed to switch the processor to process other procedures. Not until the register stores another 32 bytes data, the interrupt signal is transmitted to the processor. The step S24 is then performed to receive the interrupt signal with the processor. After that, the current processed procedure is stopped, and the step S20 is performed to access the 32 bytes data from the register. As mentioned above, this solution, which is unlike the previous solution that has to inquire the state of the register all the time, will switch to other procedures once the processor accesses the 32 bytes data from the register. Thus, on the one hand the processor must process other procedures, and on the other hand the processor must wait for the interrupt signal. As a result, the processor must process one interrupt signal for every access of 32 bytes.
Please refer to FIG. 3 and FIG. 4 for the detailed description of the conventional problems. FIG. 3 shows the disadvantage of the procedures shown in FIG. 1. The blocks 30 shown in FIG. 3 mean the time periods in which the processor accesses the data from the register in the procedure A. The blocks 32 shown in FIG. 3 mean the time periods in which the processor can not access the data, which are invalid, from the register and continuously inquires and waits the register in the procedure A. As shown in FIG. 3, once the register has new data, the processor can perform the access action immediately. After the access action, the processor inquires and waits the register again. Thus, the processor wastes a lot of time on inquiring and waiting. In other words, the total time that the processor spent on the procedure A includes many blocks 32.
FIG. 4 shows the disadvantage of the procedures shown in FIG. 2. The blocks 40 shown in FIG. 4 mean the time periods in which the processor accesses the data from the register in the procedure A. The blocks 42 shown in FIG. 4 mean the time periods in which the processor can not access the data, which are invalid, from the register in the procedure A and switches to process the procedure B. The blocks 44 shown in FIG. 4 mean the time periods in which the processor processes the procedure B. As shown in FIG. 4, if the processor can not access the valid data from the register, it switches to the procedure B. Once the processor receives an interrupt signal showing that the register has new data for the procedure A, the processor will switch to process the procedure A again and then access the data from the register. Thus, the processor wastes a lot of time on switching between the procedures. In other words, the total time that the processor spent on the procedure A includes many blocks 42.